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| mosel vitelic 1 V54C3128(16/80/40)4v(bga) 128mbit sdram 3.3 volt, bga package 8m x 16 16m x 8 32m x 4 V54C3128(16/80/40)4v(bga) rev. 1.2 september 2001 preliminary 67pc78pc system frequency (f ck ) 166 mhz 143 mhz 143 mhz 125 mhz clock cycle time (t ck3 ) 6 ns 7 ns 7 ns 8 ns clock access time (t ac3 )cas latency = 3 5.4 ns 5.4 ns 5.4 ns 6 ns clock access time (t ac2 ) cas latency = 2 5.4 ns 5.4 ns 6 ns 6 ns features 4banksx2mbitx16organization 4 banks x 4mbit x 8 organization 4 banks x 8mbit x 4 organization high speed data transfer rates up to 166 mhz full synchronous dynamic ram, with all signals referenced to clock rising edge single pulsed ras interface data mask for read/write control four banks controlled by ba0 & ba1 programmable cas latency: 2, 3 programmable wrap sequence: sequential or interleave programmable burst length: 1, 2, 4, 8 for sequential type 1, 2, 4, 8 for interleave type multiple burst read with single write operation automatic and controlled precharge command random column address every clk (1-n rule) power down mode auto refresh and self refresh refresh interval: 4096 cycles/64 ms availablein60pinwbga lvttl interface single +3.3 v 0.3 v power supply description the V54C3128(16/80/40)4v(bga) is a four bank synchronous dram organized as 4 banks x 2mbit x 16, 4 banks x 4mbit x 8, or 4 banks x 8mbit x 4. the V54C3128(16/80/40)4v(bga) achieves high speed data transfer rates up to 166 mhz by employ- ing a chip architecture that prefetches multiple bits and then synchronizes the output data to a system clock all of the control, address, data input and output circuits are synchronized with the positive edge of an externally supplied clock. operating the four memory banks in an inter- leaved fashion allows random access operation to occur at higher rate than is possible with standard drams. a sequential and gapless data rate of up to 166 mhz is possible depending on burst length, cas latency and speed grade of the device. device usage chart operating temperature range package outline access time (ns) power temperature mark b67pc78pcstd.l 0 cto70 c ? blank
2 V54C3128(16/80/40)4v(bga) rev. 1.2 september 2001 mosel vitelic V54C3128(16/80/40)4v(bga) c = cmos process sychronous dram family device number 8mbit x 16: 128164 16mbit x 8: 128804 32mbit x 4: 128404 mosel-vitelic manufactured speed v54 c 3 b 3.3v, lvttl, interface special feature 128404 6 ns 7 ns 8 ns pkg. b = wbga v = lvttl component rev. level v 60 pin wbga pin configuration top view description pkg. pin count wbga b 60 987 3 a b c d e f g h j k l m 21 987 x16 321 vccq dq0 vcc a vss dq15 vssq dq1 vssq dq2 b dq13 vccq dq14 dq3 vccq dq4 c dq11 vssq dq12 dq5 vssq dq6 d dq9 vccq dq10 dq7 nc nc e nc nc dq8 nc vcc ldqm f udqm vss vref cas we g nc clk cs ras h cke a12 ba0 ba1 j a9 a11 a10/ap a0 k a7 a8 a1 a2 l a5 a6 a3 vcc m vss a4 987 x8 321 vccq dq1 vcc a vss dq7 vssq nc vssq dq1 b dq6 vccq nc nc vccq dq2 c dq5 vssq nc nc vssq dq3 d dq4 vccq nc nc nc nc e nc nc nc nc vcc nc f dqm vss vref cas we g nc clk cs ras h cke a12 ba0 ba1 j a9 a11 a10/ap a0 k a7 a8 a1 a2 l a5 a6 a3 vcc m vss a4 987 x4 321 vccq nc vcc a vss nc vssq nc vssq dq0 b dq3 vccq nc nc vccq nc c nc vssq nc nc vssq dq1 d dq2 vccq nc nc nc nc e nc nc nc nc vcc nc f dqm vss vref cas we g nc clk cs ras h cke a12 ba0 ba1 j a9 a11 a10/ap a0 k a7 a8 a1 a2 l a5 a6 a3 vcc m vss a4 mosel vitelic V54C3128(16/80/40)4v(bga) 3 V54C3128(16/80/40)4v(bga) rev. 1.2 september 2001 capacitance* t a =0to70 c, v cc =3.3v 0.3 v, f = 1 mhz * note: capacitance is sampled and not 100% tested. absolute maximum ratings* operating temperature range .................. 0 to 70 c storage temperature range ................-55 to 150 c input/output voltage.................. -0.3 to (v cc +0.3) v power supply voltage .......................... -0.3 to 4.6 v power dissipation ..............................................1 w data out current (short circuit).......................50 ma *note: stresses above those listed under ? absolute maximum ratings ? may cause permanent damage of the device. exposure to absolute maximum rating conditions for extended periods may affect device reliability. symbol parameter max. unit c i1 input capacitance (a0 to a11) 3.8 pf c i2 input capacitance ras ,cas ,we ,cs , clk, cke, dqm 3.8 pf c io output capacitance (i/o) 6 pf c clk input capacitance (clk) 3.5 pf block diagram row decoder memory array bank 0 4096 x 512 x16bit column decoder sense amplifier & i(o) bus row decoder memory array bank 1 4096 x 512 x16 bit column decoder sense amplifier & i(o) bus row decoder memory array bank 2 4096 x 512 x16bit column decoder sense amplifier & i(o) bus row decoder memory array bank 3 4096 x 512 x16bit column decoder sense amplifier & i(o) bus input buffer output buffer i/o 1 -i/o 16 column address counter column address buffer row address buffer refresh counter a0 - a11, ba0, ba1 a0 - a8, ap, ba0, ba1 control logic & timing generator clk cke cs ras cas we ldqm row addresses column addresses udqm x16 configuration 4 V54C3128(16/80/40)4v(bga) rev. 1.2 september 2001 mosel vitelic V54C3128(16/80/40)4v(bga) block diagram x8 configuration row decoder memory array bank 0 4096 x 1024 x8bit column decoder sense amplifier & i(o) bus row decoder memory array bank 1 4096 x 1024 x8bit column decoder sense amplifier & i(o) bus row decoder memory array bank 2 4096 x 1024 x8bit column decoder sense amplifier & i(o) bus row decoder memory array bank 3 4096 x 1024 x8bit column decoder sense amplifier & i(o) bus input buffer output buffer i/o 1 -i/o 8 column address counter column address buffer row address buffer refresh counter a0 - a11, ba0, ba1 a0 - a9, ap, ba0, ba1 control logic & timing generator clk cke cs ras cas we dqm row addresses column addresses 5 V54C3128(16/80/40)4v(bga) rev. 1.2 september 2001 mosel vitelic V54C3128(16/80/40)4v(bga) block diagram x4 configuration row decoder memory array bank 0 4096 x 2048 x4bit column decoder sense amplifier & i(o) bus row decoder memory array bank 1 4096 x 2048 x4bit column decoder sense amplifier & i(o) bus row decoder memory array bank 2 4096 x 2048 x4bit column decoder sense amplifier & i(o) bus row decoder memory array bank 3 4096 x 2048 x4bit column decoder sense amplifier & i(o) bus input buffer output buffer i/o 1 -i/o 4 column address counter column address buffer row address buffer refresh counter a0 - a11, ba0, ba1 a0 - a9, a11, ap, ba0, ba1 control logic & timing generator clk cke cs ras cas we dqm row addresses column addresses 6 V54C3128(16/80/40)4v(bga) rev. 1.2 september 2001 mosel vitelic V54C3128(16/80/40)4v(bga) signal pin description pin type signal polarity function clk input pulse positive edge the system clock input. all of the sdram inputs are sampled on the rising edge of the clock. cke input level active high activates the clk signal when high and deactivates the clk signal when low, thereby initiates either the power down mode or the self refresh mode. cs input pulse active low cs enables the command decoder when low and disables the command decoder when high. when the command decoder is disabled, new commands are ignored but previous operations continue. ras ,cas we input pulse active low when sampled at the positive rising edge of the clock, cas ,ras ,andwe define the command to be executed by the sdram. a0 - a11 input level ? during a bank activate command cycle, a0-a11 defines the row address (ra0-ra11) when sampled at the rising clock edge. during a read or write command cycle, a0-an defines the column address (ca0-can) when sampled at the rising clock edge.can depends from the sdram organization: 32m x 4 sdram ca0 ? ca9, ca11. 16m x 8 sdram ca0 ? ca9. 8m x 16 sdram ca0 ? ca8. in addition to the column address, a10(=ap) is used to invoke autoprecharge operation at the end of the burst read or write cycle. if a10 is high, autoprecharge is selected and ba0, ba1 defines the bank to be precharged. if a10 is low, autoprecharge is disabled. during a precharge command cycle, a10(=ap) is used in conjunction with ba0 and ba1 to control which bank(s) to precharge. if a10 is high, all four banks will ba0 and ba1 are used to define which bank to precharge. ba0, ba1 input level ? selects which bank is to be active. dqx input output level ? data input/output pins operate in the same manner as on conventional drams. ldqm udqm input pulse active high the data input/output mask places the dq buffers in a high impedance state when sam- pled high. in read mode, dqm has a latency of two clock cycles and controls the output buffers like an output enable. in write mode, dqm has a latency of zero and operates as a word mask by allowing input data to be written if it is low but blocks the write operation if dqm is high. vcc, vss supply power and ground for the input buffers and the core logic. vccq vssq supply ?? isolated power supply and ground for the output buffers to provide improved noise immunity. 7 V54C3128(16/80/40)4v(bga) rev. 1.2 september 2001 mosel vitelic V54C3128(16/80/40)4v(bga) operation definition all of sdram operations are defined by states of control signals cs ,ras ,cas ,we ,anddqmatthe positive edge of the clock. the following list shows the thruth table for the operation commands. notes: 1. v = valid , x = don ? t care, l = low level, h = high level 2. cken signal is input level when commands are provided, cken-1 signal is input level one clock before the commands are provided. 3. these are state of bank designated by bs0, bs1 signals. 4. power down mode can not entry in the burst cycle. operation device state cke n-1 cke ncs ras cas we dqm a0-9, a11 a10 bs0 bs1 row activate idle 3 hxllhhxvv v read active 3 hxlhlhxvl v read w/autoprecharge active 3 hxlhlhxvh v write active 3 hxlhllxvl v write with autoprecharge active 3 hxlhl lxvh v rowprecharge any hxllhlxxl v precharge all any h x l l h l x x h x moderegisterset idle hxllllxvv v no operation any h x l h h h x x x x device deselect any h x h x x x x x x x auto refresh idle h h l l l h x x x x self refresh entry idle h l l l l h x x x x self refresh exit idle (self refr.) l h hxxx xxx x lhhx power down entry idle active 4 hl hxxx xxx x lhhx power down exit any (power down) lh hxxx xxx x lhhl data write/output enable active h x x x x x l x x x data write/output disable active h x x x x x h x x x 8 V54C3128(16/80/40)4v(bga) rev. 1.2 september 2001 mosel vitelic V54C3128(16/80/40)4v(bga) power on and initialization the default power on state of the mode register is supplier specific and may be undefined. the following power on and initialization sequence guarantees the device is preconditioned to each users specific needs. like a conventional dram, the synchronous dram must be powered up and initialized in a predefined manner. during power on, all vcc and vccq pins must be built up simultaneously to the specified voltage when the input signals are held in the ? nop ? state. the power on voltage must not exceed vcc+0.3v on any of the input pins or vcc supplies. the clk signal must be started at the same time. after power on, an initial pause of 200 s is required followed by a precharge of both banks using the precharge command. to prevent data contention on the dq bus during power on, it is required that the dqm and cke pins be held high during the initial pause period. once all banks have been precharged, the mode register set command must be issued to initialize the mode register. a minimum of eight auto refresh cycles (cbr) are also required.these may be done before or after programming the mode register. failure to follow these steps may lead to unpredictable start-up modes. programming the mode register the mode register designates the operation mode at the read or write cycle. this register is di- vided into 4 fields. a burst length field to set the length of the burst, an addressing selection bit to program the column access sequence in a burst cy- cle (interleaved or sequential), a cas latency field to set the access time at clock cycle and a opera- tion mode field to differentiate between normal op- eration (burst read and burst write) and a special burst read and single write mode. the mode set operation must be done before any activate com- mand after the initial power up. any content of the mode register can be altered by re-executing the mode set command. all banks must be in pre- charged state and cke must be high at least one clock before the mode set operation. after the mode register is set, a standby or nop command is re- quired. low signals of ras ,cas , and we at the positive edge of the clock activate the mode set op- eration. address input data at this timing defines pa- rameters to be set as shown in the previous table. read and write operation when ras is low and both cas and we are high at the positive edge of the clock, a ras cycle starts. according to address data, a word line of the select- ed bank is activated and all of sense amplifiers as- sociated to the wordline are set. a cas cycle is triggered by setting ras high and cas low at a clock timing after a necessary delay, t rcd ,fromthe ras timing. we is used to define either a read (we =h)orawrite(we = l) at this stage. sdram provides a wide variety of fast access modes. in a single cas cycle, serial data read or write operations are allowed at up to a 125 mhz data rate. the numbers of serial data bits are the burst length programmed at the mode set operation, i.e., one of 1, 2, 4, 8. column addresses are seg- mented by the burst length and serial data accesses are done within this boundary. the first column ad- dress to be accessed is supplied at the cas timing and the subsequent addresses are generated auto- matically by the programmed burst length and its sequence. for example, in a burst length of 8 with interleave sequence, if the first address is ? 2 ? , then the rest of the burst sequence is 3, 0, 1, 6, 7, 4, and 5. mosel vitelic V54C3128(16/80/40)4v(bga) 9 V54C3128(16/80/40)4v(bga) rev. 1.2 september 2001 address input for mode set (mode register operation) similar to the page mode of conventional dram ? s, burst read or write accesses on any col- umn address are possible once the ras cycle latches the sense amplifiers. the maximum t ras or the refresh interval time limits the number of random column accesses. a new burst access can be done even before the previous burst ends. the interrupt operation at every clock cycles is supported. when the previous burst is interrupted, the remaining ad- dresses are overridden by the new address with the full burst length. an interrupt which accompanies with an operation change from a read to a write is possible by exploiting dqm to avoid bus contention. when two or more banks are activated sequentially, interleaved bank read or write operations are possible. with the programmed burst length, alternate access and precharge operations on two or more banks can realize fast serial data access modes among many different pages. once two or more banks are activated, column to column interleave operation can be done between different pages. a11 a3 a4 a2 a1 a0 a10 a9 a8 a7 a6 a5 address bus (ax) bt burst length cas latency mode register cas latency a6 a5 a4 latency 0 0 0 reserve 0 0 1 reserve 010 2 011 3 1 0 0 reserve 1 0 1 reserve 1 1 0 reserve 1 1 1 reserve burst length a2 a1 a0 length sequential interleave 000 1 1 001 2 2 010 4 4 011 8 8 1 0 0 reserve reserve 1 0 1 reserve reserve 1 1 0 reserve reserve 1 1 1 reserve reserve burst type a3 type 0 sequential 1 interleave operation mode ba1 ba0 a11 a10 a9 a8 a7 mode 0000000 burst read/burst write 0000100 burst read/single write operation mode ba0 ba1 10 V54C3128(16/80/40)4v(bga) rev. 1.2 september 2001 mosel vitelic V54C3128(16/80/40)4v(bga) burst length and sequence: refresh mode sdram has two refresh modes, auto refresh and self refresh. auto refresh is similar to the cas -before-ras refresh of conventional drams. all of banks must be precharged before applying any re- fresh mode. an on-chip address counter increments the word and the bank addresses and no bank infor- mation is required for both refresh modes. the chip enters the auto refresh mode, when ras and cas are held low and cke and we are held high at a clock timing. the mode restores word line after the refresh and no external precharge command is necessary. a minimum trc time is re- quired between two automatic refreshes in a burst refresh mode. the same rule applies to any access command after the automatic refresh operation. the chip has an on-chip timer and the self re- fresh mode is available. it enters the mode when ras ,cas , and cke are low and we is high at a clock timing. all of external control signals including the clock are disabled. returning cke to high en- ables the clock and initiates the refresh exit opera- tion. after the exit command, at least one t rc delay is required prior to any access command. dqm function dqm has two functions for data i/o read and write operations. during reads, when it turns to ? high ? at a clock timing, data outputs are disabled and become high impedance after two clock delay (dqm data disable latency t dqz ). it also provides a data mask function for writes. when dqm is acti- vated, the write operation at the next clock is prohib- ited (dqm write mask latency t dqw = zero clocks). power down in order to reduce standby power consumption, a power down mode is available. all banks must be precharged and the necessary precharge delay (trp) must occur before the sdram can enter the power down mode. once the power down mode is initiated by holding cke low, all of the receiver cir- cuits except clk and cke are gated off. the power down mode does not perform any refresh opera- tions, therefore the device can ? t remain in power down mode longer than the refresh period (tref) of the device. exit from this mode is performed by tak- ing cke ? high ? . one clock delay is required for mode entry and exit. auto precharge two methods are available to precharge sdrams. in an automatic precharge mode, the cas timing accepts one extra address, ca10, to determine whether the chip restores or not after the operation. if ca10 is high when a read command is issued, the read with auto-precharge function is initiated. the sdram automatically enters the precharge operation one clock before the last data out for cas latencies 2, two clocks for cas laten- cies 3 and three clocks for cas latencies 4. if ca10 is high when a write command is issued, the write burst length starting address (a2 a1 a0) sequential burst addressing (decimal) interleave burst addressing (decimal) 2 xx0 xx1 0, 1 1, 0 0, 1 1, 0 4x00 x01 x10 x11 0, 1, 2, 3 1, 2, 3, 0 2, 3, 0, 1 3, 0, 1, 2 0, 1, 2, 3 1, 0, 3, 2 2, 3, 0, 1 3, 2, 1, 0 8 000 001 010 011 100 101 110 111 0 1 2 3 4 5 6 7 1 2 3 4 5 6 7 0 2 3 4 5 6 7 0 1 3 4 5 6 7 0 1 2 4 5 6 7 0 1 2 3 5 6 7 0 1 2 3 4 6 7 0 1 2 3 4 5 7 0 1 2 3 4 5 6 0 1 2 3 4 5 6 7 1 0 3 2 5 4 7 6 2 3 0 1 6 7 4 5 3 2 1 0 7 6 5 4 4 5 6 7 0 1 2 3 5 4 7 6 1 0 3 2 6 7 4 5 2 3 0 1 7 6 5 4 3 2 1 0 mosel vitelic V54C3128(16/80/40)4v(bga) 11 V54C3128(16/80/40)4v(bga) rev. 1.2 september 2001 with auto-precharge function is initiated. the sdram automatically enters the precharge opera- tion a time delay equal to t wr (write recovery time) after the last data in. precharge command there is also a separate precharge command available. when ras and we are low and cas is high at a clock timing, it triggers the precharge operation. three address bits, ba0, ba1 and a10 are used to define banks as shown in the following list. the precharge command can be imposed one clock before the last data out for cas latency = 2, two clocks before the last data out for cas latency = 3. writes require a time delay twr from the last data out to apply the precharge command. bank selection by address bits: burst termination once a burst read or write operation has been ini- tiated, there are several methods in which to termi- nate the burst operation prematurely. these methods include using another read or write com- mand to interrupt an existing burst operation, use a precharge command to interrupt a burst cycle and close the active bank, or using the burst stop com- mand to terminate the existing burst operation but leave the bank open for future read or write com- mands to the same page of the active bank. when interrupting a burst with another read or write command care must be taken to avoid i/o conten- tion. the burst stop command, however, has the fewest restrictions making it the easiest method to use when terminating a burst operation before it has been completed. if a burst stop command is issued during a burst write operation, then any residual data from the burst write cycle will be ignored. data that is presented on the i/o pins before the burst stop command is registered will be written to the memory. a10 ba0 ba1 0 0 0 bank 0 0 0 1 bank 1 0 1 0 bank 2 0 1 1 bank 3 1xx allbanks recommended operation and characteristics for lv-ttl t a =0to70 c; v ss =0v;v cc ,v ccq =3.3v 0.3 v note: 1. all voltages are referenced to v ss . 2. v ih may overshoot to v cc + 2.0 v for pulse width of < 4ns with 3.3v. v il may undershoot to -2.0 v for pulse width < 4.0 ns with 3.3v. pulse width measured at 50% points with amplitude measured peak to dc reference. parameter symbol limit values unit notes min. max. input high voltage v ih 2.0 vcc+0.3 v 1, 2 input low voltage v il ? 0.3 0.8 v 1, 2 output high voltage (i out = ? 4.0 ma) v oh 2.4 ? v output low voltage (i out =4.0ma) v ol ? 0.4 v input leakage current, any input (0 v < v in < 3.6 v, all other inputs = 0 v) i i(l) ? 55 a output leakage current (dq is disabled, 0 v < v out 13 V54C3128(16/80/40)4v(bga) rev. 1.2 september 2001 mosel vitelic V54C3128(16/80/40)4v(bga) ac characteristics 1,2, 3 t a =0to70 c; v ss =0v;v dd =3.3v0.3v,t t =1ns # symbol parameter limit values unit note -6 -7pc -7 -8pc min. max. min. max. min. max. min. max. clock and clock enable 1t ck clock cycle time cas latency = 3 cas latency = 2 6 7.5 ? ? 7 7.5 ? ? 7 10 ? ? 8 10 ? ? s ns ns 2t ck clock frequency cas latency = 3 cas latency = 2 ? ? 166 133 ? ? 143 133 ? ? 143 100 ? ? 125 100 mhz mhz 3t ac access time from clock cas latency = 3 cas latency = 2 ? _ 5.4 5.4 ? _ 5.4 5.4 ? _ 5.4 6 ? _ 6 6 ns ns 2, 4 4t ch clock high pulse width 2.5 ? 2.5 ? 2.5 ? 3 ? ns 5t cl clock low pulse width 2.5 ? 2.5 ? 2.5 ? 3 ? ns 6t t transition tim 0.3 1.2 0.3 1.2 0.3 1.2 0.5 10 ns setup and hold times 7t is input setup time 1.5 ? 1.5 ? 1.5 ? 2 ? ns 5 8t ih input hold time 0.8 ? 0.8 ? 0.8 ? 1 ? ns 5 9t cks input setup time 1.5 ? 1.5 ? 1.5 ? 2 ? ns 5 10 t ckh cke hold time 0.8 ? 0.8 ? 0.8 ? 1 ? ns 5 11 t rsc mode register set-up time 12 ? 14 ? 14 ? 16 ? ns 12 t sb powerdownmodeentrytime 06070708ns common parameters 13 t rcd row to column delay time 12 ? 15 ? 15 ? 20 ? ns 6 14 t rp row precharge time 15 ? 15 ? 15 ? 20 ? ns 6 15 t ras row active time 40 100k 42 100k 42 100k 45 100k ns 6 16 t rc row cycle time 60 ? 60 ? 60 ? 60 ? ns 6 17 t rrd activate(a) to activate(b) command period 12 ? 14 ? 14 ? 16 ? ns 6 18 t ccd cas (a) to cas (b) command period 1 ? 1 ? 1 ? 1 ? clk refresh cycle 19 t ref refresh period (4096 cycles) ? 64 ? 64 ? 64 ? 64 ms 20 t srex self refresh exit time 1 ? 1 ? 1 ? 1 ? clk 14 V54C3128(16/80/40)4v(bga) rev. 1.2 september 2001 mosel vitelic V54C3128(16/80/40)4v(bga) notes for ac parameters: 1. for proper power-up see the operation section of this data sheet. 2. ac timing tests have v il = 0.8v and v ih = 2.0v with the timing referenced to the 1.4 v crossover point. the transition time is measured between v ih and v il . all ac measurements assume t t = 1ns with the ac output load circuit shown in figure 1. 4. if clock rising time is longer than 1 ns, a time (t t /2 ? 0.5) ns has to be added to this parameter. 5. if t t is longer than 1 ns, a time (t t ? 1) ns has to be added to this parameter. 6. these parameter account for the number of clock cycle and depend on the operating frequency of the clock, as follows: the number of clock cycle = specified value of timing period (counted in fractions as a whole number) self refresh exit is a synchronous operation and begins on the 2nd positive clock edge after cke returns high. self refresh exit is not complete until a time period equal to trc is satisfied once the self refresh exit command is registered. 7. referenced to the time which the output achieves the open circuit condition, not to output voltage levels read cycle 21 t oh data out hold time 3 ? 3 ? 3 ? 3 ? ns 2 22 t lz data out to low impedance time 1 ? 1 ? 1 ? 0 ? ns 23 t hz dataouttohighimpedancetime 36373738ns7 24 t dqz dqm data out disable latency ? 2 ? 2 ? 2 ? 2clk write cycle 25 t wr write recovery time 2 ? 2 ? 2 ? 2 ? clk 26 t dqw dqm write mask latency 0 ? 0 ? 0 ? 0 ? clk # symbol parameter limit values unit note -6 -7pc -7 -8pc min. max. min. max. min. max. min. max. 1.4v 1.4v tcs tch tac tac tlz toh thz clk command output 50 pf i/o z=50 ohm +1.4v 50 ohm vih vil t t figure 1. tck ac characteristics (cont ? d) 15 V54C3128(16/80/40)4v(bga) rev. 1.2 september 2001 mosel vitelic V54C3128(16/80/40)4v(bga) timing diagrams 1. bank activate command cycle 2. burst read operation 3. read interrupted by a read 4. read to write interval 4.1readtowriteinterval 4.2 minimum read to write interval 4.3 non-minimum read to write interval 5. burst write operation 6. write and read interrupt 6.1 write interrupted by a write 6.2 write interrupted by read 7. burst write & read with auto-precharge 7.1 burst write with auto-precharge 7.2 burst read with auto-precharge 8. burst termination 8.1 termination of a burst write operation 8.2 termination of a burst write operation 9. ac- parameters 9.1 ac parameters for a write timing 9.2 ac parameters for a read timing 10. mode register set 11. power on sequence and auto refresh (cbr) 12. power down mode 13. self refresh (entry and exit) 14. auto refresh (cbr) 16 V54C3128(16/80/40)4v(bga) rev. 1.2 september 2001 mosel vitelic V54C3128(16/80/40)4v(bga) timing diagrams (cont ? d) 15. random column read ( page within same bank) 15.1 cas latency = 2 15.2 cas latency = 3 16. random column write ( page within same bank) 16.1 cas latency = 2 16.2 cas latency = 3 17. random row read ( interleaving banks) with precharge 17.1 cas latency = 2 17.2 cas latency = 3 18. random row write ( interleaving banks) with precharge 18.1 cas latency = 2 18.2 cas latency = 3 19. precharge termination of a burst 19.1 cas latency = 2 19.2 cas latency = 3 17 V54C3128(16/80/40)4v(bga) rev. 1.2 september 2001 mosel vitelic V54C3128(16/80/40)4v(bga) 1. bank activate command cycle (cas latency = 3) 2. burst read operation (burst length = 4, cas latency = 2, 3) address clk t0 t t1 t ttt command nop nop nop bank a row addr. bank a activate write a with auto bank a col. addr. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . bank b activate bank a row addr. bank a activate t rcd : ? h ? or ? l ? t rc precharge t rrd bank b row addr. command read a nop nop nop nop nop nop nop dout a 0 cas latency = 2 t ck3, i/o ? s cas latency = 3 dout a 1 dout a 2 dout a 3 nop clk t0 t2 t1 t3 t4 t5 t6 t7 t8 t ck2, i/o ? s dout a 0 dout a 1 dout a 2 dout a 3 18 V54C3128(16/80/40)4v(bga) rev. 1.2 september 2001 mosel vitelic V54C3128(16/80/40)4v(bga) 3. read interrupted by a read (burst length = 4, cas latency = 2, 3) 4.1 read to write interval (burst length = 4, cas latency = 3) command read a read b nop nop nop nop nop nop t ck2, i/o ? s cas latency = 2 t ck3, i/o ? s cas latency = 3 nop clk t0 t2 t1 t3 t4 t5 t6 t7 t8 dout b 0 dout b 1 dout b 2 dout b 3 dout a 0 dout b 0 dout b 1 dout b 2 dout b 3 dout a 0 command nop read a nop nop nop nop write b nop nop dqm dout a 0 din b 0 din b 1 din b 2 must be hi-z before the write command i/o ? s minimum delay between the read and write commands = 4+1 = 5 cycles clk t0 t2 t1 t3 t4 t5 t6 t7 t8 t dqz t dqw : ? h ? or ? l ? 19 V54C3128(16/80/40)4v(bga) rev. 1.2 september 2001 mosel vitelic V54C3128(16/80/40)4v(bga) 4.2 minimum read to write interval (burst length = 4, cas latency = 2) 4.3 non-minimum read to write interval (burst length = 4, cas latency = 2, 3) command nop bank a nop read a write a nop nop nop dqm din a 0 din a 1 din a 2 din a 3 must be hi-z before the write command t ck2, i/o ? s cas latency = 2 clk t0 t2 t1 t3 t4 t5 t6 t7 t8 nop activate 1 clk interval t dqz t dqw : ? h ? or ? l ? nop read a nop nop read a nop write b nop nop dqm din b 0 din b 1 din b 2 t ck1, i/o ? s cas latency = 2 t ck2, i/o ? s cas latency = 3 clk t0 t2 t1 t3 t4 t5 t6 t7 t8 dout a 0 ommand din b 0 din b 1 din b 2 dout a 1 dout a 0 must be hi-z before the write command t dqz t dqw : ? h ? or ? l ? 20 V54C3128(16/80/40)4v(bga) rev. 1.2 september 2001 mosel vitelic V54C3128(16/80/40)4v(bga) 5. burst write operation (burst length = 4, cas latency = 2, 3) 6.1 write interrupted by a write (burst length = 4, cas latency = 2, 3) command nop write a nop nop nop nop nop nop i/o ? s din a 0 din a 1 din a 2 din a 3 nop clk t0 t2 t1 t3 t4 t5 t6 t7 t8 extra data is ignored after the first data element and the write are registered on the same clock edge. termination of a burst. don ? t care command nop write a write b nop nop nop nop nop i/o ? s din a 0 din b 0 din b 1 din b 2 nop din b 3 clk t0 t2 t1 t3 t4 t5 t6 t7 t8 1 clk interval 21 V54C3128(16/80/40)4v(bga) rev. 1.2 september 2001 mosel vitelic V54C3128(16/80/40)4v(bga) 6.2 write interrupted by a read (burst length = 4, cas latency = 2, 3) 7. burst write with auto-precharge burst length = 2, cas latency = 2, 3) command nop write a read b nop nop nop nop nop nop t ck2, i/o ? s cas latency = 2 din a 0 t ck3, i/o ? s cas latency = 3 din a 0 clk t0 t2 t1 t3 t4 t5 t6 t7 t8 dout b 3 dout b 0 dout b 1 dout b 2 dout b 3 don ? t care don ? t care don ? t care dout b 0 dout b 1 dout b 2 input data must be removed from the i/o ? s at least one clock cycle before the read dataappears on the outputs to avoid data contention. command nop nop nop write a auto-precharge clk t0 t2 t1 t3 t4 t5 t6 t7 t8 nop bank a active nop nop din a 0 din a 1 i/o ? s cas latency = 3 i/o ? s cas latency = 2 begin autoprecharge bank can be reactivated after trp * t wr t rp din a 0 din a 1 t wr t rp nop * 22 V54C3128(16/80/40)4v(bga) rev. 1.2 september 2001 mosel vitelic V54C3128(16/80/40)4v(bga) 7.2 burst read with auto-precharge burst length = 4, cas latency = 2, 3) command nop write a read b nop nop nop nop nop nop t ck2, i/o ? s cas latency = 2 t ck3, i/o ? s cas latency = 3 clk t0 t2 t1 t3 t4 t5 t6 t7 t8 dout a 3 dout a t rp t rp * * * 0 dout a 1 dout a 2 dout a 3 dout a begin autoprecharge bank can be reactivated after t rp 0 dout a 1 dout a 2 23 V54C3128(16/80/40)4v(bga) rev. 1.2 september 2001 mosel vitelic V54C3128(16/80/40)4v(bga) 8.1 termination of a burst read operation (cas latency = 2, 3) 8.2 termination of a burst write operation (cas latency = 2, 3) command read a nop nop nop burst nop nop nop nop t ck2, i/o ? s cas latency = 2 t ck3, i/o ? s cas latency = 3 stop clk t0 t2 t1 t3 t4 t5 t6 t7 t8 dout a 0 dout a 1 dout a 2 dout a 3 dout a 0 dout a 1 dout a 2 dout a 3 command nop write a nop nop burst nop nop nop nop din a 0 din a 1 din a 2 stop clk t0 t2 t1 t3 t4 t5 t6 t7 t8 input data for the write is masked. i/o ? s cas latency = 2,3 don ? t care 24 V54C3128(16/80/40)4v(bga) rev. 1.2 september 2001 mosel vitelic V54C3128(16/80/40)4v(bga) clk cke cs i/o ras cas we ba dqm 9.1 ac parameters for write timing t2 t3 t4 t0 t1 t6 t7 t8 t9 t5 t11 t12 t13 t14 t10 t16 t17 t18 t19 t15 t22 t20 t21 hi-z ap burst length = 4, cas latency = 2 addr t cks t cs t ch t ckh t as t rcd t rc t rp t ds activate command bank a write with auto precharge command bank a activate command bank b write with auto precharge command bank b activate command bank a write command bank a precharge command bank a activate command bank a t dh ax0 ax3 ax2 ax1 bx0 bx3 bx2 bx1 ay0 ay3 ay2 ay1 t ck2 t ch t cl begin auto precharge bank a begin auto precharge bank b t dpl t rrd activate command bank b ray cbx ray ray rbx rbx cax rby rby raz raz rax rax t ah 25 V54C3128(16/80/40)4v(bga) rev. 1.2 september 2001 mosel vitelic V54C3128(16/80/40)4v(bga) \ clk cke cs i/o ras cas we ba dqm 9.2 ac parameters for read timing t2 t3 t4 t0 t1 t6 t7 t8 t9 t5 t11 t12 t13 t10 hi-z ap burst length = 2, cas latency = 2 addr t cs t ch t ckh t as t ah t rrd t rcd t ras t lz activate command bank a activate command bank b activate command bank a precharge command bank a t cks t ck2 ax0 ax1 read command bank a read with auto precharge command t rc t rp t ac2 t ac2 t oh t hz t ch t cl bx0 begin auto precharge bank b bx1 t hz rbx ray rbx rbx ray cax rax rax 26 V54C3128(16/80/40)4v(bga) rev. 1.2 september 2001 mosel vitelic V54C3128(16/80/40)4v(bga) \ 10. mode register set clk cke cs ras cas we ba t2 t3 t4 t0 t1 t6 t7 t8 t9 t5 t11 t12 t13 t14 t10 t16 t17 t18 t19 t15 t22 t20 t21 ap addr precharge command all banks mode register set command any command address key 2 clock min. 27 V54C3128(16/80/40)4v(bga) rev. 1.2 september 2001 mosel vitelic V54C3128(16/80/40)4v(bga) \ 11. power on sequence and auto refresh (cbr) clk cke cs i/o ras cas we ba dqm ttt t0 tt t tt t t t tt t1 t t tt tt t t hi-z ap addr precharge command all banks t rp minimum of 2 refresh cycles are required 1st auto refresh command t rc high level is required 2nd auto refresh command inputs must be stable for 200 s any command 2 clock min. mode register address key set command 28 V54C3128(16/80/40)4v(bga) rev. 1.2 september 2001 mosel vitelic V54C3128(16/80/40)4v(bga) \ 12. power down mode burst length = 4, cas latency = 2 clk cke cs i/o ras cas we ba dqm t2 t3 t4 t0 t1 t6 t7 t8 t9 t5 t11 t12 t13 t14 t10 t16 t17 t18 t19 t15 t22 t20 t21 hi-z ap addr t cksp rax rax activate command bank a precharge command bank a power down mode entry power down mode exit any command 29 V54C3128(16/80/40)4v(bga) rev. 1.2 september 2001 mosel vitelic V54C3128(16/80/40)4v(bga) 13. self refresh (entry and exit) ba addr ap t clk cke cs i/o ras cas we dqm t2 t3 t4 t0 t1 t t tt t5 t t tt t t t tt tt t t hi-z all banks must be idle self refresh entry begin self refresh exit command t srex self refresh exit command issued self refresh exit t rc cksr 30 V54C3128(16/80/40)4v(bga) rev. 1.2 september 2001 mosel vitelic V54C3128(16/80/40)4v(bga) \ 14. auto refresh (cbr) burst length = 4, cas latency = 2 clk cke cs i/o ras cas we ba dqm t2 t3 t4 t0 t1 t6 t7 t8 t9 t5 t11 t12 t13 t14 t10 t16 t17 t18 t19 t15 t22 t20 t21 hi-z ap addr ax0 ax1 activate command read command precharge command auto refresh command auto refresh command t rc t rp t rc t ck2 all banks cax rax rax bank a bank a ax2 ax3 (minimum interval) 31 V54C3128(16/80/40)4v(bga) rev. 1.2 september 2001 mosel vitelic V54C3128(16/80/40)4v(bga) \ ) 15.1 random column read (page within same bank) (1 of 2) burst length = 4, cas latency = 2 clk cke cs i/o ras cas we ba dqm t2 t3 t4 t0 t1 t6 t7 t8 t9 t5 t11 t12 t13 t14 t10 t16 t17 t18 t19 t15 t22 t20 t21 hi-z ap addr activate command bank a cax read command bank a cay read command bank a aw0 aw1 aw2 aw3 ax0 ax1 ay0 ay1 az0 az1 az2 az3 ay2 ay3 caw read command bank a raw raw precharge command bank a activate command bank a caz read command bank a raz raz t ck2 32 V54C3128(16/80/40)4v(bga) rev. 1.2 september 2001 mosel vitelic V54C3128(16/80/40)4v(bga) \ ) 15.2 random column read (page within same bank) (2 of 2) burst length = 4, cas latency = 3 clk cke cs i/o ras cas we ba dqm t2 t3 t4 t0 t1 t6 t7 t8 t9 t5 t11 t12 t13 t14 t10 t16 t17 t18 t19 t15 t22 t20 t21 hi-z ap addr activate command bank a cax read command bank a cay read command bank a aw0 aw1 aw2 aw3 ax0 ax1 ay0 ay1 ay2 ay3 caw read command bank a raw raw precharge command bank a activate command bank a caz read command bank a raz raz t ck3 33 V54C3128(16/80/40)4v(bga) rev. 1.2 september 2001 mosel vitelic V54C3128(16/80/40)4v(bga) \ ) 16.1 random column write (page within same bank) (1 of 2) burst length = 4, cas latency = 2 clk cke cs i/o ras cas we ba dqm t2 t3 t4 t0 t1 t6 t7 t8 t9 t5 t11 t12 t13 t14 t10 t16 t17 t18 t19 t15 t22 t20 t21 hi-z ap addr cbx write command bank b cby write command bank b precharge command bank b dbw0 dbw3 dbw2 dbw1 dbx1 dbx0 dby0 dby3 dby2 dby1 dbz0 dbz3 dbz2 dbz1 t ck2 activate command bank b cax write command bank b raw raw activate command bank b cbz write command bank b rbz rbz activate command bank b cbz write command bank b rbz rbz 34 V54C3128(16/80/40)4v(bga) rev. 1.2 september 2001 mosel vitelic V54C3128(16/80/40)4v(bga) \ ) 16.2 random column write (page within same bank) (2 of 2) burst length = 4, cas latency = 3 clk cke cs i/o ras cas we ba dqm t2 t3 t4 t0 t1 t6 t7 t8 t9 t5 t11 t12 t13 t14 t10 t16 t17 t18 t19 t15 t22 t20 t21 hi-z ap addr cbx write command bank b cby write command bank b precharge command bank b dbw0 dbw3 dbw2 dbw1 dbx1 dbx0 dby0 dby3 dby2 dby1 dbz0 dbz1 t ck3 activate command bank b cbz write command bank b rbz rbz activate command bank b cbz write command bank b rbz rbz 35 V54C3128(16/80/40)4v(bga) rev. 1.2 september 2001 mosel vitelic V54C3128(16/80/40)4v(bga) 17.1 random row read (interleaving banks) (1 of 2) burst length = 8, cas latency = 2 clk cke cs i/o ras cas we a11(bs) dqm t2 t3 t4 t0 t1 t6 t7 t8 t9 t5 t11 t12 t13 t14 t10 t16 t17 t18 t19 t15 t22 t20 t21 hi-z a10 a0 - a9 cby read command bank b read command bank a bx0 bx1 bx2 bx3 bx4 bx5 bx6 bx7 by0 by1 t ck2 high t rcd t ac2 t rp cax precharge command bank b ax0 ax1 ax2 ax3 ax4 ax5 ax6 ax7 activate command bank b rbx rbx activate command bank a rax rax cbx read command bank b activate command bank b rby rby 36 V54C3128(16/80/40)4v(bga) rev. 1.2 september 2001 mosel vitelic V54C3128(16/80/40)4v(bga) 17. 2 random row read (interleaving banks) (2 of 2) burst length = 8, cas latency = 3 clk cke cs i/o ras cas we a11(bs) dqm t2 t3 t4 t0 t1 t6 t7 t8 t9 t5 t11 t12 t13 t14 t10 t16 t17 t18 t19 t15 t22 t20 t21 hi-z a10 a0 - a9 cby read command bank b by0 t ck3 high t ac3 activate command bank b rbx rbx activate command bank a rax rax cbx read command bank b activate command bank b rby rby t rcd precharge command bank b cax read command bank a t rp bx0 bx1 bx2 bx3 bx4 bx5 bx6 bx7 ax0 ax1 ax2 ax3 ax4 ax5 ax6 ax7 precharge command bank a 37 V54C3128(16/80/40)4v(bga) rev. 1.2 september 2001 mosel vitelic V54C3128(16/80/40)4v(bga) 18.1 random row write (interleaving banks) (1 of 2) burst length = 8, cas latency = 2 clk cke cs i/o ras cas we a11(bs) dqm t2 t3 t4 t0 t1 t6 t7 t8 t9 t5 t11 t12 t13 t14 t10 t16 t17 t18 t19 t15 t22 t20 t21 hi-z a10 a0 - a9 t ck2 high t rcd t rp write command bank a cay dax0 dax3 dax2 dax1 dax4 dax7 dax6 dax5 dbx0 dbx3 dbx2 dbx1 dbx4 dbx7 dbx6 dbx5 day0 day3 day2 day1 t dpl write command bank a cax activate command bank a rax rax activate command bank b rbx rbx cbx precharge command bank a write command bank b activate command bank a ray ray cay precharge command bank b write command bank a day4 t dpl 38 V54C3128(16/80/40)4v(bga) rev. 1.2 september 2001 mosel vitelic V54C3128(16/80/40)4v(bga) 18.2 random row write (interleaving banks) (2 of 2) burst length = 8, cas latency = 3 clk cke cs i/o ras cas we a11(bs) dqm t2 t3 t4 t0 t1 t6 t7 t8 t9 t5 t11 t12 t13 t14 t10 t16 t17 t18 t19 t15 t22 t20 t21 hi-z a10 a0 - a9 t ck3 high dax0 dax3 dax2 dax1 dax4 dax7 dax6 dax5 dbx0 dbx3 dbx2 dbx1 dbx4 dbx7 dbx6 dbx5 day2 day1 day0 write command bank a cax activate command bank b rbx rbx activate command bank a ray ray day3 t dpl cbx write command bank b precharge command bank a write command bank a cay precharge command bank b t rp t dpl t rcd activate command bank a rax rax 39 V54C3128(16/80/40)4v(bga) rev. 1.2 september 2001 mosel vitelic V54C3128(16/80/40)4v(bga) 19.1 precharge termination of a burst (1 of 2) burst length = 8, cas latency = 2 clk cke cs i/o ras cas we ba dqm t2 t3 t4 t0 t1 t6 t7 t8 t9 t5 t11 t12 t13 t14 t10 t16 t17 t18 t19 t15 t22 t20 t21 hi-z ap addr t ck2 precharge command bank a dax0 dax3 dax2 dax1 precharge termination of a write burst. write data is masked. ay0 ay1 ay2 precharge termination of a read burst. precharge command bank a t rp activate command bank a rax rax write command bank a cax cay read command bank a high activate command bank a ray ray t rp activate command bank a raz raz caz read command bank a az0 az1 az2 precharge command bank a t rp 40 V54C3128(16/80/40)4v(bga) rev. 1.2 september 2001 mosel vitelic V54C3128(16/80/40)4v(bga) 19.2 precharge termination of a burst (2 of 2) burst length = 4, 8, cas latency = 3 clk cke cs i/o ras cas we ba dqm t2 t3 t4 t0 t1 t6 t7 t8 t9 t5 t11 t12 t13 t14 t10 t16 t17 t18 t19 t15 t22 t20 t21 hi-z ap addr t ck3 precharge command bank a dax0 precharge termination of a write burst. write data is masked ay0 ay1 ay2 precharge termination precharge command bank a t rp activate command bank a rax rax write command bank a cax cay read command bank a high activate command bank a ray ray t rp activate command bank a raz raz of a read burst. 41 V54C3128(16/80/40)4v(bga) rev. 1.2 september 2001 mosel vitelic V54C3128(16/80/40)4v(bga) complete list of operation commands sdram function truth table current state 1 cs ras cas we bs addr action idle h l l l l l l l x h h h l l l l x h h l h h l l x h l x h l h l x x bs bs bs bs x op- x x x x ra ap x code nop or power down nop illegal 2 illegal 2 row (&bank) active; latch row address nop 4 auto-refresh or self-refresh 5 mode reg. access 5 row active h l l l l l l x h h h l l l x h l l h h l x x h l h l x x x bs bs bs bs x x x ca,ap ca,ap x ap x nop nop begin read; latch ca; determineap begin write; latch ca; determineap illegal 2 precharge illegal read h l l l l l l l x h h h h l l l x h h l l h h l x h l h l h l x x x bs bs bs bs bs x x x x ca,ap ca,ap x ap x nop (continue burst to end;>row active) nop (continue burst to end;>row active) burst stop command > row active term burst, new read, determineap 3 term burst, start write, determineap 3 illegal 2 term burst, precharge illegal write h l l l l l l l x h h h h l l l x h h l l h h l x h l h l h l x x x bs bs bs bs bs x x x x ca,ap ca,ap x ap x nop (continue burst to end;>row active) nop (continue burst to end;>row active) burst stop command > row active term burst, start read, determineap 3 term burst, new write, determineap 3 illegal 2 term burst, precharge 3 illegal read with auto precharge h l l l l l l l x h h h h l l l x h h l l h h l x h l h l h l x x x bs bs x bs bs x x x x x x x ap x nop (continue burst to end;> precharge) nop (continue burst to end;> precharge) illegal 2 illegal 2 illegal illegal 2 illegal 2 illegal 42 V54C3128(16/80/40)4v(bga) rev. 1.2 september 2001 mosel vitelic V54C3128(16/80/40)4v(bga) sdram function truth table(continued) current state 1 cs ras cas we bs addr action write with auto precharge h l l l l l l l x h h h h l l l x h h l l h h l x h l h l h l x x x bs bs x bs bs x x x x x x x ap x nop (continue burst to end;> precharge) nop (continue burst to end;> precharge) illegal 2 illegal 2 illegal illegal 2 illegal 2 illegal precharging h l l l l l l x h h h l l l x h h l h h l x h l x h l x x x bs bs bs bs x x x x x x ap x nop;> idle after trp nop;> idle after trp illegal 2 illegal 2 illegal 2 nop 4 illegal row activating h l l l l l l x h h h l l l x h h l h h l x h l x h l x x x bs bs bs bs x x x x x x ap x nop;> row active after trcd nop;> row active after trcd illegal 2 illegal 2 illegal 2 illegal 2 illegal write recovering h l l l l l l x h h h l l l x h h l h h l x h l x h l x x x bs bs bs bs x x x x x x ap x nop nop illegal 2 illegal 2 illegal 2 illegal 2 illegal refreshing h l l l l l x h h h l l x h h l h l x h l x x x x x x x x x x x x x x x nop;> idle after trc nop;> idle after trc illegal illegal illegal illegal mode register accessing h l l l l x h h h l x h h l x x h l x x x x x x x x x x x x nop nop illegal illegal illegal 43 V54C3128(16/80/40)4v(bga) rev. 1.2 september 2001 mosel vitelic V54C3128(16/80/40)4v(bga) clock enable (cke) truth table: abbreviations: ra = row address bs = bank address ca = column address ap = auto precharge notes for sdram function truth table: 1. current state is state of the bank determined by bs. all entries assume that cke was active (high) during the preceding clock cycle. 2. illegal to bank in specified state; function may be legal in the bank indicated by bs, depending on the state of that bank. 3. must satisfy bus contention, bus turn around, and/or write recovery requirements. 4. nop to bank precharging or in idle state. may precharge bank(s) indicated by bs (andap). 5. illegal if any bank is not idle. 6. cke low to high transition will re-enable clk and other inputs asynchronously. a minimum setup time must be satisfied before any command other than exit. 7. power-down and self-refresh can be entered only from the all banks idle state. 8. must be legal command as defined in the sdram function truth table. state(n) cke n-1 cke ncs ras cas we addr action self-refresh 6 h l l l l l l x h h h h h l x h l l l l x x x h h h l x x x h h l x x x x h l x x x x x x x x x x invalid exit self-refresh, idle after trc exit self-refresh, idle after trc illegal illegal illegal nop (maintain self-refresh) power-down h l l l l l l x h h h h h l x h l l l l x x x h h h l x x x h h l x x x x h l x x x x x x x x x x invalid exit power-down, > idle. exit power-down, > idle. illegal illegal illegal nop (maintain low-power mode) all. banks idle 7 h h h h h h h h l h l l l l l l l l x h l l l l l l x x x h h h l l l x x x h h l h l l x x x h l x x h l x x x x x x x x x x refer to the function truth table enter power- down enter power- down illegal illegal illegal enter self-refresh illegal nop 44 V54C3128(16/80/40)4v(bga) rev. 1.2 september 2001 mosel vitelic V54C3128(16/80/40)4v(bga) package diagram 60-pin wbga 0.80 0.20 m s b 1.60 1.05 8.50 0.10 13.0 0.10 0.50 a 1.00 1.00 0.20 m s a b ? 0.45 0.05 out of die mark area (#2) notes: 1. no bond figure exposed 2. do not measure / / within this area s ? 0.15 m s a b // 0.2 9 min 0.10 (#1) 0.25+0.05 (#1) -0.10 ? 0.08 m s 0.12 s mosel vitelic 3910 n. first street, san jose, ca 95134-1501 ph: (408) 433-6000 fax: (408) 433-0952 tlx: 371-9461 mosel vitelic worldwide offices V54C3128(16/80/40)4v(bga) the information in this document is subject to change without notice. mosel vitelic makes no commitment to update or keep cur- rent the information contained in this document. no part of this document may be copied or reproduced in any form or by any means without the prior written consent of mosel-vitelic. mosel vitelic subjects its products to normal quality control sampling techniques which are intended to provide an assurance of high quality products suitable for usual commercial applica- tions. mosel vitelic does not do testing appropriate to provide 100% product quality assurance and does not assume any liabil- ity for consequential or incidental arising from any use of its prod- ucts. if such products are to be used in applications in which personal injury might occur from failure, purchaser must do its own quality assurance testing appropriate to such applications. ? copyright 2001, mosel vitelic inc. 9/01 printed in u.s.a. u.s. sales offices u.s.a. 3910 north first street san jose, ca 95134 phone: 408-433-6000 fax: 408-433-0952 taiwan 7f, no. 102 min-chuan e. road, sec. 3 taipei phone: 886-2-2545-1213 fax: 886-2-2545-1209 no 19 li hsin road science based ind. park hsin chu, taiwan, r.o.c. phone: 886-3-579-5888 fax: 886-3-566-5888 singapore 10 anson road #23-13 international plaza singapore 079903 phone: 65-3231801 fax: 65-3237013 japan onze 1852 building 6f 2-14-6 shintomi, chuo-ku tokyo 104-0041 phone: 03-3537-1400 fax: 03-3537-1402 uk & ireland suite 50, grovewood business centre strathclyde business park bellshill, lanarkshire, scotland, ml4 3nq phone: 44-1698-748515 fax: 44-1698-748516 germany (continental europe & israel) benzstrasse 32 71083 herrenberg germany phone: +49 7032 2796-0 fax: +49 7032 2796 22 northwestern 3910 north first street san jose, ca 95134 phone: 408-433-6000 fax: 408-433-0952 southwestern 302 n. el camino real #200 san clemente, ca 92672 phone: 949-361-7873 fax: 949-361-7807 central, northeastern & southeastern 604 fieldwood circle richardson, tx 75081 phone: 214-352-3775 fax: 214-904-9029 |
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